Blog Archive

PLATFORM REPORT: Top Energy Lab Chooses Xeon for Next-Gen Supercomputer

In this kickoff of a new video feature covering notable developments in parallel chips and computers, Contributing Editor R. Colin Johnson reports on the new, screamingly fast parallel processing supercomputer at Pacific Northwest National Laboratory (PNNL).  The yet-to-be-named new supercomputer uses Intel Xeon and Xeon Phi cores, and will aim …

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Identifying and Modeling Parallel Software: Intel’s Mark Davis previews topics and tips from the 2013 Intel Software Conference Road Show

  What are the best ways to add correct and effective parallelism to your programs? How can Intel® Advisor XE 2013 help both novices and experts? Where should you focus your efforts? Join Intel Senior Principal Engineer Mark Davis for answers to these and other related questions at his educational …

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Department of Energy Chooses Xeon Phi

  The Department of Energy’s (DoE) Environmental Molecular Sciences Laboratory (EMSL) has chosen the Intel many-integrated core (MIC) architecture with Xeon Phi coprocessors for its next-generation parallel processor at its Pacific Northwest National Laboratory (PNNL). The new supercomputer uses Intel Xeon and Xeon Phi cores, and will aim for peak …

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Acquiring mutexes in C++

The mutex system that Threading Building Blocks includes are easy to use. However, you need to understand exactly how they work so that you don’t end up with problems such as deadlocks and locks being held open. This week Jeff Cogswell shows you the starting code for mutexes. Last time …

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Independent Test: Xeon Phi Shocks Tesla GPU

Intel’s Xeon Phi coprocessor outperforms Nvidia’s Tesla graphic-processing unit (GPU) on the operations used by “solver” applications in science and engineering, according to independent tests at Ohio State University. When comparing Intel’s Xeon Phi to Nvidia’s Tesla, most reviewers dwell on how much easier it is to rewrite parallel programs …

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The C++ Secret to Making Mutexes Work

In my previous blog, we talked about the pitfalls of trying to coordinate threads in parallel programming  and relying on mutexes. When not properly handled, this can result in performance bottlenecks that are no better (or even worse) than serial algorithms. Nevertheless, you may well need to make use of …

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Neuromorphic Chips: Ultimate Parallel Processors

Purdue University is working with semiconductor researchers, including Intel research scientist Charles Augustine of its Circuits Research Lab (Hillsboro, Ore), to develop spin-based neuromorphic microchips as the ultimate parallel processors–consuming as little as 300-times less power than circuits today. Traditional semiconductor chips use electrical charge to store information, requiring thousands …

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Fujitsu Boosts HPC with Xeon Phi

The fifth ranked server manufacturer worldwide–Fujitsu Ltd.–has begun refocusing its high-performance computing (HPC) aspirations on the Xeon Phi coprocessor. Now available for its popular Primergy servers, Intel’s Xeon Phi coprocessor is changing the rules of the game for HPC, according to a Fujitsu, which claims that old-school HPCs with thousands …

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Tutorial: Intel Parallel Processors Span Gamut

Performance increases in next-generation microprocessors no longer rely on cranking clock speeds–except during Turbo Boost. Instead, speed-ups today come from parallel programming harnessing multi-core hyper-threaded processors, spanning everything from tiny mobiles to massive supercomputers. In fact, all modern Intel central processing units (CPUs) are parallel processors–from the tiny Atom to …

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From the Editor: 2013 Intel Software Conference and Go Parallel on Facebook

  This year’s four-city educational tour kicks off March 5 with the theme “Let Performance Thrive.”  The intensive one-day workshop explores the techniques and tools that can get your applications to market faster—and help increase performance and accuracy. This conference is designed for C, C++, and Fortran developers and is …

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