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- Intel Rules Supercomputer SpeedfestIntel powered four of every five screamingly fast winners in the twice-annual Top500.org ranking at the International Supercomputer Conference (ISC 2013,...
- Cray Brings Intel Hadoop Distro to CS300 SupercomputerCray is adding Intel’s flavor of Hadoop to its CS300 supercomputers. Does this mark the beginning of a new era? And what does...
- Case Study: RADVISION Boosts IP Apps for Multicore PlatformsRADVISION offers the broadest and most complete set of standards-based video networking infrastructure and developer toolkits available. But the company was...
- Octal Xeon Phi Server Hits 8-teraFLOPSWith the Xeon Phi poised to win the “world’s fastest supercomputer” crown next week coprocessors in general, and Intel’s...
- Open CASCADE Doubles PerformanceOpen CASCADE found it challenging to maximize performance in complex software simulations for its clients while eliminating errors and bottlenecks. ...
- Parallel HPC Reaches for the StarsHigh-performance parallel computing is taking off – literally. NASA and the U.S. Air Force have begun development of the Next Generation...
The Future of Parallel Software Development
Intel’s James Reinders Discusses His Two Newest Books, Parallel Programming for Xeon Phi, C and C++
Intel’s James Reinders Talks OpenMP, Developer Tools and GPUs
Embedded, Parallel Worlds Converging
HPC Drives Life Science Research at Texas Supercomputing Center
Improving Your Coding AND Professional Craft
Case Studies
Evaluation Guides
Tech Documents
Tutorials
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- Intel Rules Supercomputer Speedfest
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Blog Archive
The C++ Secret to Making Mutexes Work
In my previous blog, we talked about the pitfalls of trying to coordinate threads in parallel programming and relying on mutexes. When not properly handled, this can result in performance bottlenecks that are no better (or even worse) than serial algorithms. Nevertheless, you may well need to make use of …
Neuromorphic Chips: Ultimate Parallel Processors
Purdue University is working with semiconductor researchers, including Intel research scientist Charles Augustine of its Circuits Research Lab (Hillsboro, Ore), to develop spin-based neuromorphic microchips as the ultimate parallel processors–consuming as little as 300-times less power than circuits today. Traditional semiconductor chips use electrical charge to store information, requiring thousands …
Fujitsu Boosts HPC with Xeon Phi
The fifth ranked server manufacturer worldwide–Fujitsu Ltd.–has begun refocusing its high-performance computing (HPC) aspirations on the Xeon Phi coprocessor. Now available for its popular Primergy servers, Intel’s Xeon Phi coprocessor is changing the rules of the game for HPC, according to a Fujitsu, which claims that old-school HPCs with thousands …
Tutorial: Intel Parallel Processors Span Gamut
Performance increases in next-generation microprocessors no longer rely on cranking clock speeds–except during Turbo Boost. Instead, speed-ups today come from parallel programming harnessing multi-core hyper-threaded processors, spanning everything from tiny mobiles to massive supercomputers. In fact, all modern Intel central processing units (CPUs) are parallel processors–from the tiny Atom to …
From the Editor: 2013 Intel Software Conference and Go Parallel on Facebook
This year’s four-city educational tour kicks off March 5 with the theme “Let Performance Thrive.” The intensive one-day workshop explores the techniques and tools that can get your applications to market faster—and help increase performance and accuracy. This conference is designed for C, C++, and Fortran developers and is …
New “Must Read” on High Performance Parallel Programming
For more than two years Intel’s James Reinders and Jim Jeffers circled the globe, teaching and gathering real-life experiences and best practices into a foundational new book, Intel® Xeon Phi™ Coprocessor High Performance Programming. Go Parallel Editor Joe Maglitta sat down with Reinders to talk about the scope, challenges …
Water-Cooled Parallel Processors Use MIC
Water-cooled parallel processors based on Intel’s Many Integrated Core (MIC) architecture are boosting performance and cutting energy consumption in Russian research centers. Common to all the Russian parallel processors, including that of the previously announced Russian Academy of Sciences, is direct-liquid cooling of their Xeon and Xeon Phi cores …
Russian Supercomputer Adopts Xeon Phi
The Russian Academy of Science is aiming for the region’s fastest supercomputer in a joint effort with the Commonwealth of Independent States (CIS, formerly the Soviet Republics). By harnessing thousands of parallel Intel Xeon and Xeon Phi cores, the 10 petaFLOPS JSCC supercomputer will advance the frontiers of Soviet …
Dividing Data with Cilk Plus
If you’ve been following my articles, you know you can use Threading Building Blocks (TBB) with blocked ranges to divide work into parallel chunks. That works well with TBB. But what about Cilk Plus? Cilk Plus gives you less control over how your work is divided up. The tradeoff is …
Vector-Based and Deterministic Parallel Programming
In the latest installment of the series, Intel Principal Engineer and author Michael McCool explains the mechanisms for expressing vector parallelism, both explicitly and implicitly, and the central role of Intel’s CILK Plus. You’ll also better understand the distinction between determinism and non-determinism, and more. (5:30)