- Parallel Success Starts With Proper Planning“Measure twice; cut once.” That maxim of carpentry is also good advice for parallel programming, according to a recent technical paper...
- Best, Brightest Parallel Students Work for “Betterment of Life on Earth”Who will help create the next-generation of faster, higher resolution parallel computing models to help counter climate change, global warming and...
- Wanted: Energy-Efficient SupercomputersWho says super-fast computing has to be energy-wasting computing? That challenging question is at the core of a discussion workshop on...
- Data Deluge Bottlenecking BreakthroughsData complexity and lack of scalability of underlying algorithms is bottlenecking the nation’s ability to analyze and apply massive amounts of...
- Barcelona Supercomputing Center Joins OpenMP boardBarcelona Supercomputing Center (BSC) has joined the OpenMP Architecture Review Board (ARB), a consortium of 24 vendors and research organizations creating...
- $1,734 Helps You Master Parallel UniverseMystified by aspects of parallel computing? You’re not alone. But take heart. Advance orders are being taken on Amazon.com for...
Embedded, Parallel Worlds Converging
HPC Drives Life Science Research at Texas Supercomputing Center
Improving Your Coding AND Professional Craft
Meeting New Challenges of Scaling Parallelism Across and Within Cores
Parallel Platform Report: Believe it – Affordable HPC is Here
Xeon Phi Powers HPC Stampede
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- Parallel Success Starts With Proper Planning
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Blog Archive
Atom “Clover Trail” Tailored for Windows 8
Intel’s Atom “Clover Trail” processor (Z2760) is custom-tailored for Window 8 to provide drastically extended battery lifetime of mobile devices and tablets, according to Technology Showcase presenters at the recent MEMS Executive Congress. “The Atom Z2760, code-named Clover Trail, was architected from the ground up for Windows 8,” explains …
Hawking’s ‘Big Brain’ Powered by Intel MIC
The world’s first symmetric multi-processor (SMP) to be powered by Intel’s Many Integrated Core (MIC) architecture is also the latest incarnation of Stephen Hawking’s pioneering Cosmos supercomputer for the Miracle Consortia. Cosmos makes use of SGI’s “Big Brain”–the SGI UV 2000–which houses 32 Xeon Phi co-processors utilizing a total …
Ask James Reinders: The Push/Pull of Hardware and Software Evolution
Leading edge insight, views and explanation from James Reinders, Director, Software Evangelist, Intel Corporation. Conducted by Geeknet Contributing Editors Jeff Cogswell and John Jainschigg. Geeknet: I was reading through some recent presentations of yours – in particular the presentation you did for the Texas Advanced Computing Center, back in …
Intel FFT Paper Wins Award at SC12
SC12, supercomputing.org’s U.S. conference, held recently in Salt Lake City, UT, drew some of the best and brightest in scientific, engineering and enterprise supercomputing and HPC together to share ideas, view new tech and solutions, and (gently) compete for the benefit of science and the industry. On Nov.15, Intel …
Performance Tuning with VTune Amplifier XE
Intel’s Senior Staff Software Engineer Gary Carleton tells how you can identify and eliminate bottlenecks in mixed or single language applications. Learn how Intel’s VTune Amplifier XE helps analyze CPU usage and other metrics and much more. For an example and deeper dive on how you can tune applications, …
Xeon Phi Wins Top 10 Supercomputer Slot
Intel’s massively parallel Xeon Phi coprocessor powered a Top 10 Supercomputer on the 20th anniversary of the Top500 Supercomputer List. At 2.6-petaFLOPS, Stampede ranked seventh out of 500 supercomputers, one of only 23 petaflop-caliber systems on this year’s list. Located at the Texas Advanced Computing Center at the University …
SSDs: Keys to Multicore Speed
A few weeks back we spoke with Intel’s Walter Shands on using Intel VTune Amplifier 2013 to optimize HMMER, a molecular biology package, written in Fortran. The main point outlined in Shand’s Intel webinar October 16: VTune Amplifier can significantly improve multicore performance of algorithmically complex, purpose-specific code while …
Maximum Performance, Minimum Effort: Optimizing Legacy Code for the Latest Intel® Architectures
How do you most effectively unlock the power of more cores and wider vectors? Noah Clemons, Technical Consulting Engineer, Intel Corp. and Edward Nugent, Research Intern, Naval Postgraduate School sit down with Geeknet Senior Content Director Joe Maglitta and explain how, along with the key role of Intel® Parallel Studio XE 2013 and …
Creating Starter and Continuing Graph Nodes with Threading Building Blocks
Last week we talked about the general concepts behind the graph mechanism in Threading Building Blocks (TBB). This week I want to show you some code. We’ll spend the next couple of weeks working on this, because there’s more than we can fit into a single blog. Let’s start with …
Parallel Programing: Goals, Skills, Platforms, Markets, Languages
How are software developers and their organizations adapting to new parallel computing architectures? How broad is the market for parallelism, software acceleration and optimization? What platforms are organizations deploying products on, and for what languages do developers need parallel programming support? Read this informative research report today and find out …

