Earlier this week — on June 18, the opening day of the International Supercomputing Conference (ISC) in Hamburg — Intel officially announced their widely anticipated coprocessor series based on the MIC (Many Integrated Cores) architecture. Previously dubbed “Knight’s Corner,” the new 50+ core Xeon Phi, due for delivery later this year and based on Intel’s new 22nm process and 3-D tri-gate transistor architecture, will ride to market in a dual-slot PCIe 3.0 board with 8GB+ of GDDR5 RAM, offering a full TeraFLOP of double-precision floating-point performance.
Calling the coprocessor Xeon Phi helps make clear to the general HPC market what’s already stridently obvious to industry analysts and computer scientists lucky enough to have access to pre-production Knights Corner prototypes: this chip may change HPC and supercomputing in a big way. It’s going to do so, at least in the short term, less by exemplifying brand new technology (which it does), and more by simply “being a Xeon.”
As Intel’s release makes clear, a major point of Xeon Phi is that its many-core power can be accessed simply, both by desktop applications and in cluster configurations, by making relatively trivial directive-level changes in software sources that can be built, compiled, tested and substantially optimized today for deployment on Xeon multicore CPUs and clusters. Intel’s release on Xeon Phi proves the point by incorporating multiple C/C++ and Fortran code examples, including OpenMP, Fortran co-arrays, Intel Array Building Blocks, Intel Threading Building Blocks, MPI, OpenCL and Math Kernel Library — all tools and programming models available today, and widely accepted by the target HPC engineering and scientific computing community.
This high level of forward compatibility with existing code significantly lowers barriers to entry, and should power rapid adoption of Xeon Phi. As Dan Stanzione, Deputy Director of the Texas Advanced Computing Center of the University of Texas at Austin put it, “Moving a code to Intel Xeon Phi might involve sitting down and adding a couple lines of directives that takes a few minutes.” By contrast, “… Moving a code to a GPU is a project.” Stanzione articulates a major problem with otherwise highly-performant GPU-based coprocessors: their complexity and unique architectures compel developers to climb a significant learning curve, increase project costs and limit architectural flexibility.
On-hand for the Intel announcement at ISC, Cray Inc. co-announced that their upcoming “Cascade” supercomputer line, slated for 1H 2013 delivery, will be able to use Xeon Phi as soon as the coprocessors are available. The Cascade program describes a supercomputer with a flexible architecture that optimizes for message-passing, array processing and other paradigms, and derives in part from Cray’s participation in DARPA’s High Productivity Computing Systems project, which seeks to broaden access to supercomputing by enabling very high performance while reducing the requirement for ultra-specialized code development and close adaptation of software to hardware platforms.