Most Recent Tune Posts RSS

Two Ways to Put Transactional Synchronization Extensions into Play

Intel has provided two distinct ways to implement Transactional Synchronization Extensions (TSX). The first is by using a new set of operations that won’t run on older processors. The second is to use older operations that have been reworked with the new technology. Jeff Cogswell explores how this works. Intel’s …

Read Full Post Posted in Tune | Leave a comment

Build Robust Systems Using Flow Graph in TBB

Much effort has gone into enabling software to take advantage of the increase in computing power in modern parallel machines, but most software available today offer limited scalability. Find out the importance of building robust systems by mapping the actor/agent paradigm to your algorithm or code and implementing the system …

Read Full Post Posted in Build | Leave a comment

What Parallel Pros Need to Know About Transaction Synchronization Extensions

Intel introduced Transactional Synchronization Extensions (TSX) with its Haswell architecture, which came out in 2013. In this two-part series, Jeff Cogswell explains the rationale behind TSX and how it can help in your parallel programming. In the first of this two-part series, I’m going to discuss a technology in Intel …

Read Full Post Posted in Tune | Leave a comment

Better Android App Building with Intel C++ Compiler

While most Android apps are written in Java, a large number of developers use C or C++ and use Android NDK to build the shared library and Java Native Interface (JNI). App performance, including a smooth user experience, is one of the key reasons for using native programming over Java. …

Read Full Post Posted in Tune | Leave a comment

Exploring the Xeon Phi Coprocessor Architecture

The Xeon Phi Coprocessor ships as an entire board that you can plug into an existing computer. In this video, Jeff Cogswell explores the architecture of this board, including the processor itself, the flash memory, the main memory, and the system controller.

Read Full Post Posted in Tune | Leave a comment

Xeon Phi Coprocessor Memory Matters

In order to get the most out of the many cores of the Xeon Phi coprocessor, each of which supports four physical threads, the right kind of memory and an operating system—either Linux or Windows—are required. In this blog, Jeff Cogswell explains how the memory and operating system are architected. …

Read Full Post Posted in Design | Leave a comment

Using Windows Instead of Linux as a Host for Xeon Phi Coprocessor

Although much of the documentation for the Xeon Phi Coprocessor mentions Linux as the host computer, Intel also includes drivers for Windows. Jeff Cogswell explains how this works, and how the coprocessor itself still uses Linux in such cases. A reader recently asked about whether you can use a Xeon …

Read Full Post Posted in Design | Leave a comment

Bust Bottlenecks with Powerful MPI Software Tool

The new 9.0 Beta release of the Intel Trace Analyzer and Collector, which is a profiler that helps you understand MPI application behavior and effectively visualize bottlenecks in your code, introduces an even easier way to identify performance issues with a new tool called the Performance Assistant. Find out how …

Read Full Post Posted in Tune | Leave a comment

Xeon Phi Developer Training From the Experts

Intel has announced a software developer training series for the Xeon Phi coprocessor. The one-day trainings are taking place in more than 30 major cities in the U.S. and Canada through September. The course will provide software developers the foundation needed for modernizing their code to take advantage of parallel …

Read Full Post Posted in Tune | Leave a comment

Build Both Vectorized and Multicore Code in Cilk Plus

Cilk Plus usually focuses on multicore programming. But each core has its own set of registers, which means you can also accomplish vectorization alongside multicore programming. Jeff Cogswell shows you how.

Read Full Post Posted in Tune | Leave a comment