In the latest installment of the series, Intel Principal Engineer and author Michael McCool explains the mechanisms for expressing vector parallelism, both explicitly and implicitly, and the central role of Intel’s CILK Plus. You’ll also better understand the distinction between determinism and non-determinism, and more. (5:30)
- Two Ways to Put Transactional Synchronization Extensions into PlayIntel has provided two distinct ways to implement Transactional Synchronization Extensions (TSX). The first is by using a new set of...
- What Parallel Pros Need to Know About Transaction Synchronization ExtensionsIntel introduced Transactional Synchronization Extensions (TSX) with its Haswell architecture, which came out in 2013. In this two-part series, Jeff Cogswell...
- Vectorization 101: Getting Back to the BasicsIn this video, Jeff Cogswell introduces the concept of vectorization. He shows how the processor can do mathematical operations on entire...
- Better Android App Building with Intel C++ CompilerWhile most Android apps are written in Java, a large number of developers use C or C++ and use Android NDK...
- Painlessly Port Apps to Intel Xeon Phi CoprocessorThe huge benefits of having the Intel Xeon Phi coprocessor as a programming platform are widely known within the development community....
- How Intel Security Could Stop Another HeartbleedA newly formed consortium has been set up to build security for Internet of Things could backstop open-source as well. McAfee,...
- Two Ways to Put Transactional Synchronization Extensions into Play
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Calendar of Events
- April 29 -- Performance essentials using OpenMP* 4.0 vectorization with C/C++ -- 9 AM PT -
- May 1 -- Xeon Phi Developer Training: An Intro to Efficient Parallel Programming - at Los Angeles
- May 6 -- Flow Graph with Intel® Threading Building Blocks -- 9 AM PT -
- May 6 -- Xeon Phi Developer Training: An Intro to Efficient Parallel Programming - at Phoenix/Tucson, AZ
- May 13 -- Find Bugs Quickly and Easily in Your Fortran Application Using Intel® Inspector XE -- 9 am PT -
- May 14 -- Xeon Phi Developer Training: An Intro to Efficient Parallel Programming -- Raleigh, NC -
- May 20 -- Tachyon ray tracer port on Intel® Xeon Phi™ coprocessor -- 9 AM PT -
- May 20 -- Xeon Phi Developer Training: An Intro to Efficient Parallel Programming -- San Francisco -
- June 3 -- Intel® VTune™ Amplifier XE Overview and New Features -- 9 AM PT -
- June 3 -- Xeon Phi Developer Training: An Intro to Efficient Parallel Programming - at Pittsburgh